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ACS714
Chopper Stabilization Technique
Automotive Grade, Fully Integrated, Hall Effect-Based Linear Current Sensor IC
with 2.1 kVRMS Voltage Isolation and a Low-Resistance Current Conductor
Chopper Stabilization is an innovative circuit technique that is
used to minimize the offset voltage of a Hall element and an asso-
ciated on-chip amplifier. Allegro patented a Chopper Stabiliza-
tion technique that nearly eliminates Hall IC output drift induced
by temperature or package stress effects. This offset reduction
technique is based on a signal modulation-demodulation process.
Modulation is used to separate the undesired DC offset signal
from the magnetically induced signal in the frequency domain.
This technique is made possible through the use of a BiCMOS
process that allows the use of low-offset and low-noise amplifiers
in combination with high-density logic integration and sample
and hold circuits.
Regulator
Clock/Logic
Then, using a low-pass filter, the modulated DC offset is sup-
pressed while the magnetically induced signal passes through
the filter. As a result of this chopper stabilization approach, the
Hall Element
Amp
Low-Pass
Filter
output voltage from the Hall IC is desensitized to the effects
of temperature and mechanical stress. This technique produces
devices that have an extremely stable Electrical Offset Voltage,
are immune to thermal stress, and have precise recoverability
after temperature cycling.
Concept of Chopper Stabilization Technique
Typical Applications
+5 V
V PEAK
+5 V
C BYP
0.1 μF
C2
0.1 μF
V RESET
C BYP
0.1 μF
R1
100 kΩ
IP+
R3
330 kΩ
IP+
I P
1
2
3
4
VCC
IP+ VIOUT
ACS714
IP– FILTER
IP–
GND
8
7
6
5
R F
10 kΩ
C OUT
0.1 μF
V OUT
R1
1 MΩ
C F
1 nF
R2
33 kΩ
R4
10 kΩ
U1 D1
LT1178 1N914
C1
0.1 μF
Q1
2N7002
I P
1
2
3
4
VCC
IP+ VIOUT
ACS714
IP– FILTER
IP–
GND
8
7
6
5
R2
100 kΩ
R F
1 kΩ
C F
0.01 μF
1
3
LM321
5
4
2
R3
3.3 kΩ
V OUT
C1
1000 pF
Application 3. This configuration increases gain to 610 mV/A
(tested using the ACS714ELC-05A).
Application 2. Peak Detecting Circuit
+5 V
+5 V
C BYP
C BYP
0.1 μF
R1
33 kΩ
IP+ VIOUT
IP– FILTER
IP–
R1
IP+
I P
0.1 μF
1 VCC
IP+
2
ACS714
3
4
GND
8
7
6
5
V OUT
R F
2 kΩ
10 kΩ
C F
1 nF
D1
1N4448W
C1
A-to-D
Converter
I P
1
2
3
4
VCC
IP+ VIOUT
ACS714
IP– FILTER
IP–
GND
8
7
6
5
R2
100 kΩ
V OUT
C F
1 nF
4
3
–
+
R PU
100 kΩ
5
1 Fault
2 U1
LMV7235
D1
1N914
Application 4. Rectified Output. 3.3 V scaling and rectification application
for A-to-D converters. Replaces current transformer solutions with simpler
ACS circuit. C1 is a function of the load resistance and filtering desired.
R1 can be omitted if the full range is desired.
Application 5. 10 A Overcurrent Fault Latch. Fault threshold set by R1 and
R2. This circuit latches an overcurrent fault and holds it until the 5 V rail is
powered down.
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
15
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
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